Research and Development Projects

We are working in the following research areas with different local and international partners.

Vaccine Monitoring Microchip

This project is based on a ground-breaking idea of using a CMOS wirelessly-powered microchip immersed directly in the vaccine to regularly monitor vaccine's fidelity from manufacturing to delivery. The global burden due to ineffective vaccines is in billions of USD and is one of the major issues in healthcare sector. This IC contains a novel wireless power transfer based on resonant power transfer concept with customized inductors especially designed for power-transfer at 200MHz. This IC also contains an ultra-low-power Temperature Sensor in Subthreshold operating region of the MOSFET with a power consumption of sub-nW. Several patents and publications are being applied through this project.

Realtime Pathogen detector System

This project is based on the idea of removing the time-hurdle in the real-time detection of a pathogen in out-of-the-lab settings without expensive instruments to open up the possibility of mass-scale domestication. The core of this project is based on a BioMEMS IC with a pathogen-sensitive capacitive-front-end and a low-power, low-noise signal-pickup chain followed by a wireless communication stack. This project is focused on detecting both air-borne and water-borne pathogens in public places or inside houses and communicating the detection of pathogen to the neighboring smart devices to trigger a preventive response. 

A Reconfigurable 2Gbps LVDS Transceiver 150nm/110nm CMOS

This project is based the design of Low-Voltage Differential-Signaling IOs (LVDS) in 150nm and 110nm CMOS processes for Flat-Panel Display operating at 2Gbps data-rate. LVDS signaling is now extensively used in Physical layers of numerous electronic components signaling over a longer physical medium to save power at higher data-rates. 

IO Circuit Design for 2.5D Through-Silicon-Interposer Interconnects

2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as through-silicon-interposer (TSI) communication. This interposer die allows connections between adjacently-placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections.  When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25cm), TSI interconnects are much shorter (few mm) in length, which is one of the main reasons for their enhanced performance. For example, at 5Gbps a 25cm long PCB track suffers from approximately 20dB additional channel loss as compared to a 3mm long TSI. On the other hand, when compared with a TSV, a 3mm TSI interconnect approximately incurs a 70ps propagation delay with negligible increase in power consumption per unit length [11]. However, to take full advantage of the benefits offered by TSI, a multifaceted design challenge must be resolved to reach mass production, including the circuit and system design for the functional components of a 2.5D system witha customized approach to address area, power and performance issues together in the 2.5D design space to avoid over/under-design. As an example, the IO design for 2.5D die-to-die (D2D) communication, which is the main focus of this paper, falls between the IO design for PCB tracks and on-chip interconnect as the track lengths on the interposer are relatively smaller than PCB tracks and larger than the on-chip interconnects.

A PVT tolerant Current Reference Generator

A current reference circuit is an essential part of every autonomous IO limited integrated circuit. The mostly used approach to generate a stable current is to employ an external (off-chip) precision resistor with tolerance in ppm and produce a fixed voltage across this resistor through internal (on-chip) circuitry. Off-chip resistor is necessitated by the fact that on-chip resistors suffer from relatively large (20-30%) tolerances and therefore are not suitable for generating a stable reference current using this simple technique. In certain IO-limited applications, current variations in a simplistic on-chip current reference circuit due to PVT variations cause specification violation and in worst case outright functional failure. Therefore, it necessitates for a PVT tolerant compensated precision current reference to be designed for application specific integrated circuits.

Ultra-Low Power Temperature Sensor

This project focusses on subthreshold circuit design for ultra-low-power temperature sensing. It is based on direct temperature to frequency conversion using ultra-low-power VCOs. A supply and process invariant temperature sensing in subthreshold region is one of the main design challenges. Combining temperature sensing and VCO in a single loop is also the mai focus of this work. 

Enhanced Wireless Power Transfer

This work is focused on enhancing wireless power transfer techniques from different angles. One of the ideas being explored extensively is to avoid rectifier losses and devise a rectifier-less WPT circuit. Another angle shifts focus from the rectifier towards the wireless transmitter and attempts to apply chaotic signals to improve peak-to-average-power-ratio (PAPR) and therefore efficiently turn on/off the rectifying devices. 

Data Converters

This activity involves fusion of different types of data-converters architecture to take advantage of scattered yet effective architectural features. One of the main focus of this activity is on Successive Approximation ADC design while combining sub-ranging, interleaving and noise-shaping to achieve data-rates above Gbps with a resolution above 10bits and pJ/conversion FoM.

Monolithic CMOS MicroSystems for Structural , Chemical and Bio Hazard Detection

This project focuses on structural-, chemical- and bio-hazard detection/prediction using a smart fusion of micro-sensor-systems, monolithically integrated inside a CMOS microchip, suitable as an autonomous sensing-node of a wireless-sensor-network (WSN). The proposed sensor-fusion includes MEMS accelerometers, IR absorption based MEMS chemical sensors, Microcantilever based Bio-MEMS sensors and Microbolometer based low-cost IR imagers along with their configurable readout Microelectronics. The main aim is to utilize the upcoming trend of FAB-supported monolithic Microsystems manufacturing, i.e. micro-sensors and micro-electronics inside the same CMOS die without or minimal post-processing of the manufactured silicon. This monolithic integration enables the realization of a low-cost, low-power, compact, robust and high performance system, which is batch-producible in millions. The proposed  Microsystem design is not only limited to designing micro-sensors inside a CMOS process but the design of their electronic readout interfaces (ROI) is also an essential part. The applications of such a miniaturized multi-sensor system would include WSN scenarios; employed for the monitoring of structures, ambience and environment. The multi-sensor perspective helps to develop a context aware understanding of the scenario, which is a fundamentally useful aspect for the upcoming trends such as Internet-of-Things. For that reason, the correlation of the Microsystems’ specifications with the existing/emerging application paradigms necessitates for low-power profile, small foot-print, high transduction sensitivities and low production costs. A monolithically integrated system can better address these multifaceted specifications together by optimally exploiting the design-space instead of a discrete-component based sensor-system depending on generic off-the-shelf components.

 

 

High-Speed IO design for DDR3/4 PHY

 

Currently DRAM interfaces incorporate a parallel single Ended signaling due to pin-out restrictions and backward compatibility [1-3]. So far the efforts to increase data rate of single ended signaling focus either on physical design and optimization, cross-talk cancellation techniques, noise reduction through encoding and supply insensitive design as well as decaps on bandwidth enhancement through equalization [4]. GDDR5, for instance, has achieved beyond 5Gbps using Data-Bus-Inversion (DBI), data training and data equalization. This, however, is leading the system to a fundamental limit to the performance set by cross talk, which eventually results in increased system cost due to additional components such as cross-talk equalizers [5] or other bandwidth improvement techniques [8-9] or because of increased inter-wire distances and shielding. Techniques such as parallel channels or fully buffered DIMMs are used to fulfill speed and capacity demands but again at the expense of system cost [1]. In due course, differential signaling with high speed serial IO enhancements is expected to potentially take over IO performances scaling post-DDR4. Another trend which is being exercised currently is to employ multi-mode transceivers in a PHY [7] to support multiple signaling standards using a single PHY. DDR4 and post-DDR4 future trends are moving towards a point to point configuration in which driver and receiver will have one-to-one interconnection.

This activity focuses on the design of  combo DDR3 and DDR4 transceiver as part of a complete IO library containing power, ground and Vref IO cells.

RF Transceiver Design for 5G

This project aims at answering an important open question related to the effective spectrum usage in the physical layer of the 5th Generation (5G) mobile systems by incorporating an In-band Full-Duplex (IBFD) transceiver architecture. FD radio technology, where the devices transmit and receive signals simultaneously at the same center frequency, is the new breakthrough in wireless communications. This unconventional scheme for radio links promises to theoretically double the spectral efficiency compared to conventional Half-Duplex (HD) systems. A possible implication of such a revolutionary approach in wireless communications is that the cellular networks can effectively reduce their spectrum requirements by half. Moreover, advantages in higher network layers as well such as: low latency, collision prevention and security has drawn significant attention in the design of IBFD systems.

The biggest obstacle in the path of practical realization and implementation of small and low cost IBFD transceivers is the strong in-band interference, also termed as self-interference (SI). The self-interference is a result of either incorporating a single antenna for both transmission/reception or employing separate but closely spaced antennas, as a result of which the transmit signal couples strongly to the receive path. Fig.1 illustrates the different paths from which the transmit signal can couple to the receiver and saturate it. This coupling can be 60−100 dB stronger than the desired received signal, depending on the transmitted power and antenna isolation. In principle the SI can be completely cancelled at the receiving end, prior to low noise amplification, by subtracting the already known transmitted data within the device from the received signal.

The SI cancellation, however, is not as straightforward as it appears to be, since the original transmitted signal radiating from the antenna experiences various amounts of attenuation and delays, depending on the channel characteristics between the transmitter and the receiver, before falling into the receiver as linear SI components. Moreover, the non-linearities associated with the transmitting chain particularly that of the Power Amplifier (PA) generates harmonic contents which also fall in the receiver along with the linear SI components. The non-linearities associated with the receiver is also a matter of concern, as the transceiver non-linearities can mix with each other and generate intermodulation and cross modulation distortion products. To make matters worse the transmitter noise generated by high power components in the transmitting chain referred to as broadband noise increases the receiver’s noise floor to levels as high as 40−50 dB.